Design of an efficient binary phase-shift keying based IEEE 802.15.4 transceiver architecture and its performance analysis

<span lang="EN-US">The IEEE 802.15.4 <a name="_Hlk109306810"></a>physical layer (PHY) standard is one of the communication standards with wireless features by providing low-power and low-data rates in personal area network (WPAN) applications. In this paper, an efficient digital transceiver hardware architecture designed using binary phase-shift keying (BPSK) technique. The mainly has transmitter receiver modules along error calculation unit. BPSK modulation demodulation are a frequency synthesizer (DFS). DFS used to generate in-phase (I) quadrature-phase (Q) signals also provides better system performance than conventional voltage-controlled oscillator (VCO) look up table (LUT) based memory methods. differential encoding-decoding mechanism incorporated recover bits effectively reduce complexity. simulation results illustrated find bits. design utilizes less chip area, works at 268.2 MHz, consumes 108 mW total power. latency 3.5 clock cycles throughput 76.62 Mbps. bit rate (BER) 2×10-5 achieved proposed suitable for real-time work compared existing similar approaches improvement parameters.</span>